The course is prepared by Industry Expert “Anshuman Anand“.
Anshuman Anand is a semiconductor design professional, with almost two decades of experience in the VLSI Industry. In his journey in the semiconductor landscape, Anshuman has delivered multiple digital ASIC silicons in various capacities. He has worked with leading EDA companies and design houses. A technologist at heart, he has a special passion for Design Flow Methodologies, SoC Implementation, and Physical Design. In this course, he will share his multiple years of experiential learnings in Physical Design, where he has seen technology shrink firsthand from 180nm to 22nm.
(Anshuman Anand’s Linkedin profile – https://www.linkedin.com/in/anshuman-anand-5155562)
The course covers following details
- Design planning – flat vs hierarchical – considerations, partitioning, timing budgeting
- Data input – input criteria for starting physical design
- Floor-planning consideration -Macro placement, pin placement, pad ring design, power switch placement consideration
- Power planning – design of the power grid, IREM considerations, signal vs power routing considerations
- Placement – placement readiness, pre-cts considerations during placement, special physical cell placement consideration, reset tree and high-fanout network design, congestion analysis
- Clock tree design – clock tree specs, insertion delay and skew considerations, low power clock tree design, H-tree design, clock tree cell selection
- Post CTS Optimisation – setup/hold fixing planning
- Routing – global vs track routing considerations, advanced timing fixing at track assignment, design routing, post route timing correlation
- Design handoff – design handoff consider for timing and physical Signoff
- ECO planning – timing and functional eco considerations and execution
- Advanced hardening techniques – concurrent clock and data optimization, xor gating for power reduction, clock tree layer promotions etc.
