By Vikas Sachdeva
Live Webinar
September 3rd 9:30am to 1:00pm India time
Payment link for Indian Customers
Payment link for Overseas Customers
Industry Expert: Vikas Sachdeva (Vikas Sachdeva is a semiconductor design professional with more than 17 years of experience in the VLSI Industry. He has worked in design, development and deployment of multiple static and constraints products. )
What you will get
- Opportunity to learn and ask questions from the best in the Industry
- Lifetime access to webinar recording and notes.
- A course completion certificate
The webinar will covers all basic & advanced concepts in Timing Constraints
- Role of timing constraints in Timing Analysis
- Timing Constraints Overview
- Clock Definitions, create clock command with detailed explanation of all options
- Generated clock definition, create generated clock command with detailed explanation of all options
- Clock Groups command, with detailed explanation of all options
- Clock characteristics with detailed explanation of all options
- Port delays with detailed explanation of all options
- Additional boundary constraints with detailed explanation of all options
- Path specification methods with detailed explanation of all options
- False path command with detailed explanation of all options
- Multicycle path command with detailed explanation of all options
- Max and Min delay commands with detailed explanation of all options
- Disable timing with detailed explanation of all options
- Case analysis command with detailed explanation of all options
- set sense command with detailed explanation of all options
- Miscellaneous constraints command with detailed explanation of all options
- Constraints concepts related to Modes and Corners
- Constraint budgeting concepts
- Constraint promotion concepts
- Constraints verification concepts
- Mode merging of constraints concepts
- Implementation vs STA constraints concepts
- Clock Tree Synthesis (CTS) related constraints concepts
