Basics of STA and Timing Constraints – Live Webinar (Video Course)

Webinar Details

Webinar Duration: 5hrs
Date & Time: August 6th 9:30 am IST (24th July 9:00 pm PST)

Payment link for Indian Customers

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Payment link for Overseas Customers

Industry Expert: Vikas Sachdeva (Vikas Sachdeva is a semiconductor design professional with more than 17 years of experience in the VLSI Industry. He has worked in design, development and deployment of multiple static and constraints products. )

What you will get

Opportunity to learn and ask questions from the best in the Industry
Lifetime access to webinar recording and notes.
A course completion certificate

The webinar will cover all basic concepts in Static Timing Analysis and Timing Constraints

Introduction to Static Timing Analysis
Timing Paths
Startpoint, Endpoint, Combinational Logic
Setup and Hold Check Definition
Understanding details of setup slack calculation
Multiple types of Timing Paths
Design Rule Checks
Timing checks on Async Pins
Clock Gating Checks
Timing Latches
STA in presence of Multiple Clocks
Timing Arcs
Cell Delays and Models
Impact of clock network on STA
Understanding Text Report in STA
Overview of SDC
Clock and Generated Clock Definitions
Clock Groups
Clock Characteristics Specification
Port Delays
Timing Exceptions
Other SDC commands

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