CDC Design, Methodology, Constraints and Verification Workshop

Learn everything about CDC and become a Pro in 5 days!

Sample Video
YouTube player
YouTube player
YouTube player

Vikas Sachdeva


Video & Written Content
Interactive Live QA
Assignments and Labs


In this program you will get access to:

  • 8 hours of training videos access for the lifetime
  • Access to reading material with sample codes for the lifetime
  • 1hr Q/A sessions every day of the workshop
  • Telegram Cohort Group for the duration of the workshop to ask questions doubts
  • Assignments and labs to with instructor help
  • Certificate after completion of the course

Workshop Outline

Day1: Basics of CDC

Day1: Theory

  • Introduction
  • Synchronous and Asynchronous Clocks
  • Synchronizers
  • MTBF Basics
  • Deepdive into Synchronizers
  • Effects of Metastability
  • Glitch on synchronizers
  • Pulse width on Synchronizers

Day1: Labs & Quizzes

  • Defining and Identifying synchronous and Asynchronous clocks in Design & SDC
  • Reviewing lab designs and identifying any metastability issues
  • Reviewing lab designs and identifying & correcting mistakes in synchronizers
  • Quiz
Day2: Handshake Basics

Day2: Theory

  • Open and Closed Loop synchronizers
  • Passing multiple signals across clock domains
  • Synchronize Counters
  • Data path synchronization
  • Basics of FIFOs
  • Reset paths
  • CDC Verification

Day2: Labs & Quizzes

  • Design and code open loop synchronizers
  • Design and Code passage of multiple signals and buses using signal consolidation
  • Design and Code passage of multiple signals and buses using synchronized enable
  • Design and Code passage of multiple signals and buses using pulse synchronizer
  • Design a reset synchronizer
  • Quiz
Day3: Advanced CDC Part1

Day3: Theory

  • Metastability inside a flop detailed understanding
  • Mitigating CDC issues
  • Different depth synchronizers
  • MTBF Advanced Details
  • Calculate MTBF for IP, Subsystem, Chip
  • The three edge requirement
  • Pulse synchronizer detailed
  • Open and Closed loop handshake with/without ack in detail

Day3: Labs & Quizzes

  • Design handshakes to ensure 3 edge requirements
  • Design handshakes to ensure data stability
  • Open and Closed loop with ack handshake design
  • Quiz
Day4: Advanced CDC Part2

Day4: Theory

  • Multiclock FIFO Design and Verification
  • Hidden assumptions in FIFO
  • Gray encoding and counters

Day4: Labs & Quizzes

  • Design a single clock synchronous FIFO
  • Design a multi clock synchronous FIFO
  • Design a multi clock asynchronous FIFO
  • Quiz
Day5: Advanced CDC Part3

Day5: Theory

  • CDC Verification with Static Tools
  • CDC Verification with Simulation
  • CDC Verification with assertions
  • Backend CDC Verification
  • Ensuring netlist if glitch free
  • Impact of DFT Paths
  • Gate level simulations tips (x propagation removal) and recommended methods
  • Physical effects of CDC
  • Handling physical effects in STA using timing constraints

Day5: Labs & Quizzes

  • Create model for randomization on synchronizer
  • Write assertions for pulse width, data stability and glitch
  • Write FIFO assertions
  • Write timing constraints for skew on buses
  • Write timing constraints for handshake synchronization
  • Quiz

Instructor Profile

Vikas SachdevaSee LinkedIn profile

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