Learn everything about STA and become a Pro in 10 days!
Next Cohort: 28th October to 6th November

Video & Written Content

Interactive Live QA

Assignments and Labs
Features:
In this program you will get access to:
- 10 hours of training videos access for the lifetime
- Access to reading material with sample codes for the lifetime
- 1.5hr Q/A sessions every day of the workshop
- Telegram Cohort Group for the duration of the workshop to ask questions doubts
- Assignments and labs to with instructor help
- OpenSTA tool access on our cloud platform
- Certificate after completion of the course

Workshop Outline
Day1: Basics of STA
Day1: Theory
- Introduction
- STA Definitions
- Timing Paths
- Timing Path Elements
- Setup and Hold Checks
- Slack Calculation
- SDC Overview
- Clocks
- Generated Clocks
- Boundary Constraints
Day1: Labs & Quizzes
- OpenSTA Introduction
- Understanding Basics of OpenSTA
- Inputs to OpenSTA
- Constraints Creation
- OpenSTA runscipt
Day2: Other Timing Checks
Day2: Theory
- Other timing checks
- Design Rule Checks
- Latch Timing
- STA Text Report
Day2: Labs & Quizzes
- Liberty files and understanding lib parsing
- Understanding SPEF file and SPEF parsing
- Understanding timing reports
Day3: Multiple Clocks
Day3: Theory
- Multiple Clocks
- Timing arcs and Timing sense
- Cell delays and clock network
- Setup and Hold Detailed
- STA Text reports
Day3: Labs & Quizzes
- Understanding full reg to reg timing analysis
- Understanding slack computation
- Understanding and reviewing setup check report
Day4: Crosstalk and Noise
Day4: Theory
- Crosstalk and noise
- Operating modes and other variations
- Clock gating checks
- Checks on Async pins
Day4: Labs & Quizzes
- Understanding clock gating checks
- Understanding async pin checks
Day5: Clock groups
Day5: Theory
- Clock groups
- Clock properties
- Timing exceptions
- Multiple modes
Day5: Labs & Quizzes
- Revisit Slack computation
- Understand CRPR
- ECO insertion
Day6: Advanced STA – 1
Day6: Theory
- STA at different design phases
- Slew merging
- Path timing reports
- Clock network reports
- Bottleneck analysis
- Standard cell libraries
- Library attributes and modeling
- Prelayout and postlayout STA
- Glitch and noise analysis
- Inside a flop – Setup time, Hold Time, Negative setup time, Negative hold time
- Clock Gating checks
- Active High and Active Low
- Clock Gating checks on Mux
Day6: Labs & Quizzes
- Understand hold slack computation
- Multiple mode constraints file and STA
- Merged mode constraints and timing
Day7: Advanced STA – 2
Day7: Theory
- Virtual clocks and usage
- Design rule checks
- Clock uncertainty, latency and insertion delays
- Understanding query commands, netlist object access, get_* commands
- Cells, Nets and other attributes
- Timing path attributes
- Tracing commands
- Objects and Collections
- Timing report sections
- Understanding setup reports
- Debug setup violations
- Fix setup violations
- Understanding hold reports
- Debug hold reports
- Fix hold violations
- Understand and Debug Half cycle paths
- Changes with setup multicycle path
- Changes with hold multicycle path
- PVT Corners
- Multimode multi corner analysis
- On chip variations – setup and hold
- Statistical STA
- Process and Interconnect variation
- Hierarchical STA and models
- Generated clock blockage, usage of clock sense
- Sanity checks and warnings
- No paths found
- Large delays and transition times
- Missing multicycle hold
- Path not optimized
- Useful skew
- Graph based analysis vs Path based analysis
- Hold timing checks, clear conceptual understanding
- How is hold timing edge identified
Day7: Labs & Quizzes
- Multiple clocks and adding multicycle paths
- Half cycle paths debug
- Debugging no paths
- Latch timing analysis
- Signoff checklist
Day8: STA on RISC-V Based SoC
Day9: Case Study DDR Timing Closure
Day10: Revisit Fixing setup and hold violations
Instructor Profile
Vikas Sachdeva – See LinkedIn profile