Complete Timing Constraints (SDC) Workshop

Sample Video

Vikas Sachdeva

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Features:

In this program you will get access to:

• 4 hours of training videos access for the lifetime
• Access to reading material with sample codes for the lifetime
• 1 hr Q/A sessions every day of the workshop
• Telegram Cohort Group for the duration of the workshop to ask questions doubts
• Assignments and labs to with instructor help
• Certificate after completion of the course

Workshop Outline

Day1

• 🌟 Introduction and Overview
• Emphasize the practical applications of timing constraints in ensuring design integrity and performance.
• Timing Constraints Overview: Set the stage for detailed discussions by highlighting the role of timing constraints in various digital design scenarios. 📚
• 📖 Detailed Topics Coverage
• ⏰ Clock Definitions and Commands
• Create Clock Command 🛠️
• Generated Clock Definition 🔧
  
• 🕒 Clock Management Commands
• Clock Groups Command 📈
• Clock Characteristics 📉
  
• 🚦 Timing Constraints for Ports and Paths
• Port Delays ⚡
• Path Specification Methods 🛤️
• False Path and Multicycle Path Commands 🚫

Day2

• 📐 Advanced Constraint Commands
• Max and Min Delay Commands ⏱️
• Disable Timing 🚷
• Case Analysis and Set Sense Commands 🕵️
• 📋 Constraint Management and Verification
• Miscellaneous Constraints Command 📌
• Constraints Related to Modes and Corners 🔄
• Constraint Budgeting, Promotion, and Verification 💼
  
• Advanced Topics in Constraints
• Mode Merging of Constraints
• Implementation vs STA Constraints 🆚
• Clock Tree Synthesis (CTS) Related Constraints 🌲

Day3

• 📉 DDR Constraints Case Study
  Overview: Introduction to DDR memory and its unique timing constraints challenges. 🧠
  Application: Detailed exploration of DDR timing constraints. 🕵️‍♂️
  Outcomes: Discussion on the impact of correctly applied DDR constraints. 🎯
  
• 🚀 RISC-V SoC Constraints
  Overview: Introduction to the RISC-V architecture and SoC design complexities. 🧩
  Application: Examination of timing constraints specific to a RISC-V SoC. 🔍
  Outcomes: Insights into optimizing RISC-V SoC performance and power consumption. 💡
  
• 📈 Constraints Promotion Case Study
  Overview: Explanation of constraint promotion and its significance. 📊
  Application: A real-world example of constraint promotion. 🎓
  Outcomes: Understanding the benefits of effective constraint promotion. 🏆