Prerequisite: Digital Design with Verilog
The course covers the following topics
- Introduction
- Packages
- Declarations
- Variables
- Variables initialization
- Literal Values
- Built in data types
- Sequential logic
- Type casting
- Constants
- User defined types
- Enumerated types
- Arrays
- Structures
- Unions
- Packed arrays
- Unpacked arrays
- Array operations
- Combinational blocks
- Latch blocks
- Sequential blocks
- Tasks
- Functions
- Operators
- For loop
- do while loop
- foreach loop
- continue, break and return
- case statement
- priority case
- unique and priority
- unique if else
- priority if else
- Modeling FSMs
- Nested modules
- Implicit port connections
- aliasing
- Reference port
- Interfaces
- modports
- System verilog design examples
- Synthesis guidelines
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