The course covers the following topics
- Introduction
- A simple example
- Structural Description
- Behavioral Process
- Testbench
- Configuration
- Entity
- Architecture
- Processing of VHDL Code
- Comments
- Numbers, characters, strings
- Objects
- Data Types
- Operators
- Concurrent signal assignments
- Conditional signal assignment
- Mux
- Binary decoder
- Priority Encoder
- Simple ALU
- Synthesis examples
- Selected signal assignment
- Mux
- Binary decoder
- Priority Encoder
- Simple ALU
- Synthesis examples
- Conditional vs Selected
- Sequential Statements
- Process
- Wait statement
- Sequential Assignment
- Variable assignment
- If statement
- Conditional vs if
- Incomplete branch
- Incomplete assignment
- Case statement
- For loop
- Synthesis of VHDL Codes and limitations
- Inout ports
- “-” value
- Addsub design
- Comparator design
- Barrel shifter
- Priority encoder
- Signed addition
- D Latch
- D Flip Flop
- Negative edge triggered
- DFF with enable
- Shift register
- Sequence detector
- Binary counter
- Mod10 counter
- Mod-m counter
- Gray Counter
- Ring counter
- LFSR
- Register file
- FIFO
- FSMs
- Memory controller FSM
- Arbiter
- Hierarchical Design
- Components
- Generic
- Configuration
- Library
- Package
- Subprogram
- Parameterized Design
- For generate statements
- Conditional generate statements
- EXIT and NEXT
- Leading zero counting
- 2D data type
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