Digital Design With Verilog Workshop

Learn to design digital logic in Verilog like a Pro in 4 days!

Next Cohort: 4-7th August

Sample Video
YouTube player

Vikas Sachdeva

.

Video & Written Content
Interactive Live QA
Assignments and Labs

Features:

In this program you will get access to:

  • 8 hours of training videos access for the lifetime
  • Access to reading material with sample codes for the lifetime
  • 1hr Q/A sessions every day of the workshop
  • Telegram Cohort Group for the duration of the workshop to ask questions doubts
  • Assignments and labs to run on EDA playground with instructor help
  • Certificate after completion of the course

Price: Early bird pricing, valid only for short time!

India: Rs 9999 discounted to Rs 3999

Global: $139 discounted to $59.95

Course Outline

Day1: Introduction, Datatypes & Operators

Day1: Theory

  • Introduction
  • Verilog Basics – Verilog Design Styles
  • Verilog Basics – Dataflow Design
  • Verilog Basics – Behavioral Design
  • Verilog Basics – Structural Design
  • Verilog Basics – 1 bit full adder design with multiple design styles
  • Verilog Basics – Verilog Testbench
  • Designing Combinational Logic – 4 Valued Logic
  • Designing Combinational Logic – Number represenation
  • Designing Combinational Logic – Bit & Bus
  • Designing Combinational Logic – Naming conventions
  • Designing Combinational Logic – Bitwise operators
  • Designing Combinational Logic – Arithmatic operators
  • Designing Combinational Logic – Logical operators
  • Designing Combinational Logic – Relational operators
  • Designing Combinational Logic β€“ Reduction Operators
  • Designing Combinational Logic – Shift Operators
  • Designing Combinational Logic – Concatenation operators
  • Designing Combinational Logic – Repetition operators
  • Designing Combinational Logic – Conditional operators

Day1: Labs

  • Getting started with edaplayground
  • Dataflow based Design and Testbench for one bit half adder in Verilog
  • Behavioral Design and Testbench for one bit half adder in Verilog
  • Structural Design and Testbench for one bit half adder in Verilog
  • Dataflow based Design and Testbench for one bit full adder in Verilog
  • Behavioral Design and Testbench for one bit full adder in Verilog
  • Structural Design and Testbench for one bit full adder in Verilog
  • Verilog code which shows usage of all operators with $display or $monitor statements
  • Create a verilog task for conversion of Celsius into Fahrenheit (Β°C to Β°F)
  • Getting started with edaplayground
  • Dataflow based Design and Testbench for one bit half adder in Verilog
  • Behavioral Design and Testbench for one bit half adder in Verilog
  • Structural Design and Testbench for one bit half adder in Verilog
  • Dataflow based Design and Testbench for one bit full adder in Verilog
  • Behavioral Design and Testbench for one bit full adder in Verilog
  • Structural Design and Testbench for one bit full adder in Verilog
  • Verilog code which shows usage of all operators with $display or $monitor statements
  • Create a verilog function for conversion of Celsius into Fahrenheit (Β°C to Β°F)

Day2: Combinational Logic

Day2: Theory

  • 4 bit full adder design with testbench
  • 2:1 and 4:1 multiplexer design
  • 2Γ—4,3Γ—8,4Γ—2 encoder and priority encoder design
  • 4-bit Comparator Design
  • 8-bit Barrel Shifter (Combinational Left & Right)
  • Designing Arithmetic & Logic Unit (ALU)

Day2: Labs

  • Dataflow based Design and Testbench for 4 bit full adder in Verilog
  • Design and Testbench for 2:1 Mux in Verilog
  • Design and Testbench for 4:1 Mux in Verilog
  • Design and Testbench 2×4 Decoder in Verilog
  • Design and Testbench 4×2 Encoder in Verilog
  • Design and Testbench 4×2 Priority Encoder in Verilog
  • Design and Testbench 4 bit comparator in Verilog
  • Design and Testbench 8 bit barrel shifter in Verilog
  • Design and Testbench ALU in Verilog

Day3: Sequential Design

Day3: Theory

  • Clock, D-Latch and a D-Flip Flop
  • D-Flip Flop vs D-Latch
  • D-Latch with Asynchronous Reset (Behavioral)
  • D-Flip Flop (Basic)
  • Positive Edge Triggered D-Flip Flop with Asynchronous Active High Reset
  • Negative Edge Triggered D-Flip Flop with Asynchronous Active High Reset
  • Positive Edge Triggered D-Flip Flop with Asynchronous Active Low Reset
  • Positive Edge Triggered D-Flip Flop with Asynchronous Active High Set
  • D-Flip Flop with Active High Synchronous Reset
  • D-Flip Flop with Active Low Synchronous Reset
  • D-Flip Flop with Reset and Synchronous Set
  • Synchronous and Asynchronous Reset Design
  • 8-bit Twin Register Set

Day3: Labs

  • Design D-Latch in Verilog
  • Design D-Latch with Asynchronous Reset in Verilog
  • Design D-Flip Flop (Basic) in Verilog
  • Design Positive Edge Triggered D-Flip Flop with Asynchronous Active High Reset in Verilog
  • Design Negative Edge Triggered D-Flip Flop with Asynchronous Active High Reset in Verilog
  • Design Positive Edge Triggered D-Flip Flop with Asynchronous Active Low Reset in Verilog
  • Design Positive Edge Triggered D-Flip Flop with Asynchronous Active High Set in Verilog
  • Design D-Flip Flop with Active High Synchronous Reset in Verilog
  • Design D-Flip Flop with Active Low Synchronous Reset
  • Design D-Flip Flop with Synchronous Reset and Set
  • Synchronous and Asynchronous Reset Design
  • Design 8-bit Twin Register Set in Verilog

Day 4: Complex Sequential Logic and State Machines

Day4: Theory

  • Designing a 5-bit Left to Right Shift Register
  • Designing a 5-bit Universal Shift Register
  • Designing a basic counter
  • Writing a Test Bench for a Counter
  • Designing an Up Counter with Load Option
  • Designing an Up or Down Counter
  • Designing a Modulus Counter
  • Designing a Range Up Counter
  • Designing a Range Up or Down Counter with Load Option
  • Designing a Clock Frequency Divider (Divide by 2)
  • Designing a Clock Frequency Divider (Divide by 4)
  • Designing a Clock Frequency Divider (Divide by 3)
  • Designing a Single Clock First In First Out (FIFO)
  • Designing a Dual Clock First In First Out (FIFO)
  • Memory Array Options and Definitions
  • Single Port Ram
  • Dual Port Ram
  • True Dual Port Ram
  • Mealy vs Moore Machine
  • Mealy – 101 Non-Overlapping Sequence Detector
  • Mealy – 101 Overlapping Sequence Detector
  • Moore – 101 Non-Overlapping Sequence Detector
  • Moore – 101 Overlapping Sequence Detector
  • Misc.

Day4: Labs

  • Design a 5-bit Left to Right Shift Register in Verilog
  • Designing a 5-bit Universal Shift Register in Verilog
  • Designing a basic counter in Verilog
  • Writing a Test Bench for a Counter in Verilog
  • Designing an Up Counter with Load Option and Testbench in Verilog
  • Designing an Up or Down Counter with testbench in Verilog
  • Designing a Modulus Counter with testbench in Verilog
  • Designing a Range Up Counter with testbench in Verilog
  • Designing a Range Up or Down Counter with Load Option with testbenc in Verilog
  • Designing a Clock Frequency Divider (Divide by 2) in Verilog
  • Designing a Clock Frequency Divider (Divide by 4) in Verilog
  • Designing a Clock Frequency Divider (Divide by 3) in Verilog
  • Designing a Single Clock First In First Out (FIFO) in Verilog
  • Designing a Dual Clock First In First Out (FIFO) in Verilog
  • Mealy – 101 Non-Overlapping Sequence Detector with testbench in Verilog
  • Mealy – 101 Overlapping Sequence Detector with testbench in Verilog
  • Moore – 101 Non-Overlapping Sequence Detector with testbench in Verilog
  • Moore – 101 Overlapping Sequence Detector with testbench in Verilog

Instructor Profile

Vikas SachdevaSee LinkedIn profile

India: Rs 9999 discounted to Rs 3999

Global: $139 discounted to $59.95

Message Us on WhatsApp