Meticulously designed and expertly delivered
In this program we will learn & design:
- Understand VLSI Flow
- Unix for VLSI engineer
- Fundamentals of Logic Design
- Digital Design with Verilog
- Introduction to functional verification
- Introduction to SVA and functional coverage
- Assertions for synchronous FIFO
- Assertions for Asynchronous FIFO
- Assertions for ALU
- Assertions for RAM
- Assertions for the program counter
- Assertions for FSM
- Introduction to formal verification
- Gate level simulation
- UART Concepts and Verification
How the internship will be delivered
- The internship will be virtual and self-paced
- Live instructor’s help on WhatsApp and Google Meet
- The usual duration is 4 weeks
Tools
- Ubuntu Unix
- Icarus Verilog/ Cadence Xcelium/ Mentor Questa for Simulation
How the course will be taught
- Students will get project and internship certificates after finishing the course
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vlsideepdive.com 