The course covers the following topics
- Introduction
- Hardware Description Languages (HDL)
- HDL Coding Styles
- RTL Design Guidelines
- Guidelines for Naming
- Guidelines Reset and Clocks
- Sync/Async Resets
- Register initialization
- Blocking vs non blocking
- Coding style to avoid latches
- Multiple always blocks vs FSMs
- What is logic synthesis?
- Why do logic synthesis?
- Goals of Logic Synthesis
- Synthesis flow
- Libraries and Standard Cells
- Generic Logic Libraries
- Technology Specific Logic Libraries
- Clock cells
- ECO Cells
- Physical Aware synthesis
- Boolean techniques and minimization
- Timing Constraints for synthesis
- Timing paths (I/O, reg to reg)
- Area and Power constraints
- Driving Cells
- Technology Mapping
- Examples: Encoder Synthesis
- Operators synthesis
- Arithmetic Expressions synthesis
- Other Verilog constructs synthesis
- Control and Datapath synthesis
- How is clock gating inferred?
- Resizing, Cloning and Buffering
- Decomposition and Swapping
- Retiming
- DFT and Scan readiness
- Scan synthesis
- Synthesis timing reports
- Post synthesis output data
- SCAN-DEF
- Common gotchas
- Assigns statements handling in netlist
- Special characters in netlist
- change_names
- bit blasting
- uniquify
- Equivalence checking
- Equivalence checking for clock gating
- Summary
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