Prerequisite: Basic Tcl (Link)
It will cover the following topics
- Counting patterns in a string, and using STA tool commands, use of exec, redirect, regexp
- Counting cells using control flow, math functions, and procs
- Generate runtime metrics like cputime, memory
- Strings, list and pattern matching – reading all Verilog files in synthesis tool, report to list
- File handling and procs – defining proc attributes, writing and reading timing reports, read and write log files
- Tcl arrays and dictionary and more procs – setting clock periods in arrays and using for timing constraints, default proc arguments, optional arguments, parse proc arguments, proc attributes, non positional arguments
- Tcl best practices – command and argument parsing, grouping with “ or {}., rigid or weak grouping, checking variable exists, backslash substitution, variable substitution, eval, command substitution,
- Tcl scripts common gotchas – white spaces, backslashes, square brackets, incorrect weak (“) grouping, list commands some need $ some not, matching braces even when commented, {} to delimit variable name,
- Collections – Common mistakes and applications, how many clocks in my design, design objects and types, collection commands, loops in collection, getting value, iterate, collection vs list,
- Collection attributes and applications – report design statistics, tips to save tool memory, debug sta violations, create your own timing report procs, report flops,
- Filer and sort collections – report leaf cells, get sequential cells, operators allowed in filtering, get all inout ports, get don’t touch cells, get fastest clock frequency, find all attributes, find wns to a library cell,
- STA attributes and using them – timing path attributes, path groups, get timing paths with slack lesser than a certain value and find which of those belong to a certain clock, get timing paths from certain input ports with a particular clock domain, eval command, get cells in a timing path,
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