In this program you will get:
- Recorded lectures of around 6 hours for lifetime access
- Assignments and labs as homework
- Certificate after completion of the course
The course covers the following topics
- RISCV fundamentals
- Architectural State and Instruction Set
- Design process
- Microarchitectures
- Performance analysis
- Single cycle processor
- Single cycle datapath
- Single cycle control
- Adding more instructions
- Multicycle processor (datapath, control, adding more instructions)
- Pipelined processor (datapath, control, hazards)
- Design and walkthrough of RTL (verilog) of single cycle processor line by line
- Line by line testbench walkthrough of single cycle processor
- Advanced microarchitecture
- Deep pipelines
- Branch prediction
- Superscaler processors
- Out of order processor
- Multithreading concepts
- Multi core concepts
- Line by line RTL walkthrough of ibex RISC-V core
- Line by line verification and testbench walkthrough of ibex RISC-V core
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