RISC-V RTL to GDS

In this program we will learn & design:

Understand VLSI Flow
Understand basics of processor design
RISCV Fundamentals
Unix for VLSI engineer
Installation and understanding of open source EDA tool chain
A single cycle RISC-V Processor in system verilog
Write testbenches to verify the RISC-V core in system verilog
Verify the core using open source simulator verilator
Understand synthesis concepts
Understand basics of Tcl to write backend scripts
Understand basics of timing constraints
Write timing constraints to synthesize the core
Synthesize and convert the core to gate level with open source Yosys tool on 130nm technology node
Run gate level simulation to verify design on synthesized netlist
Understand dft concepts
Add dft logic to synthesized netlist using open source tool ‘Fault‘
Run complete Place and Route flow to generate GDS using OpenRoad
Write Tcl scripts to completely automate the RTL-GDS flow
Add support one more instruction in RTL and run the automated flow