RISC-V Skilling Internship

In this program we will learn & design:

• Understand VLSI Flow
• Understand the basics of processor design
• RISC-V Fundamentals
• Unix for VLSI engineer
• Fundamentals of Logic Design
• Digital Design with Verilog
• A single-cycle RISC-V Processor in system verilog
• Write test benches to verify the RISC-V core in system verilog
• Understand synthesis concepts
• RISC-V Core synthesis with Yosys
• Basics of STA
• Understand the basics of Tcl to write backend scripts
• RISC-V Core Sta Signoff using openSTA

How the internship will be delivered

• The internship will be virtual and self-paced
• Live instructor’s help on WhatsApp and Google Meet
• The usual duration is 6-8 weeks

Tools

• Ubuntu Unix
• Icarus Verilog/ Cadence Xcelium/ Mentor Questa for Simulation
• Yosys for synthesis
• OpenSTA for STA

How the course will be taught

• Students will get project and internship certificates after finishing the course

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Click on whatsapp link below to book