STA Advanced Concepts Course (Video Course)

The course is prepared by Industry Experts. This is an advanced course.

Prerequisite: Understanding of basic STA and SDC concepts

The course covers the following topics

  • Static Timing Analysis Flow
  • Required Input Files
  • Limitations of STA
  • STA at different design phases
  • Terminologies
  • Data Arrival Time
  • Data Required Time
  • Slack
  • Types of Analysis
  • Modes and Corners
  • Propagation delay
  • Slew
  • Slew merging
  • Skew between signals
  • Timing arcs and unateness
  • Max and Min timing paths
  • Clock domains
  • Operating conditions
  • All violations
  • Analysis Coverage
  • Path timing reports
  • Clock network reports
  • Bottleneck analysis
  • Standard cells libraries
  • Library attributes and modelling
  • Pin capacitance
  • Timing modelling
  • Arcs modelling
  • Noise modelling
  • Power modelling
  • Cell and Net delay calculation
  • Pre layout
  • Post Layout
  • Combinational and sequential paths
  • Multiple paths
  • Output transition calculation
  • Parasitic
  • SPEF Format
  • SDF Format
  • Crosstalk
  • Glitch analysis
  • Noise analysis
  • Crosstalk delay
  • Inside a flop – Setup time, Hold Time, Negative setup time, Negative hold time
  • Inside a flop – Clock to Q delay, Metastability
  • Timing constraints and clock properties
  • Modelling external environment
  • Virtual clocks and usage
  • Design rule checks
  • Clock uncertainty, latency and insertion delays
  • Pre layout STA and Post-layout STA
  • Breaking timing arcs
  • Path segmentation
  • Input to output feedthrough paths
  • Understanding query commands, netlist object access, get_* commands
  • Cells, Nets and other attributes
  • Timing path attributes
  • Tracing commands
  • Objects and Collections
  • Timing report sections
  • Understanding setup reports
  • Debug setup violations
  • Fix setup violations
  • Understanding hold reports
  • Debug hold reports
  • Fix hold violations
  • CRPR
  • Understand and Debug Half cycle paths
  • Understand Multiple clocks Analysis
  • Fast to slow
  • Slow to fast
  • Changes with setup multicycle path
  • Changes with hold multicycle path
  • Integer multiple
  • Non integer multiple
  • Phase shifted
  • Negedge triggered flops
  • Some example reports and explanations
  • Time borrowing
  • Conceptual understanding
  • Understand timing reports
  • Data to data checks
  • Non sequential checks
  • Clock Gating checks
  • Active High and Active Low
  • Clock Gating checks on Mux
  • Inverted clocks
  • Design Rules and other STA checks
  • Sign-off Methodology
  • Operating modes
  • PVT Corners
  • Multimode multi corner analysis
  • On chip variations – setup and hold
  • Derates
  • Statistical STA
  • Process and Interconnect variation
  • Hierarchical STA and models
  • ETM
  • Liberty
  • ILM
  • Hyperscale
  • Scope based etc.
  • Tips for Debugging STA results
  • Validate complete and correct constraints
  • Generated clock blockage, usage of clock sense
  • Sanity checks and warnings
  • No paths found
  • Clock crossing domain
  • Inverted generated clocks
  • Large I/O delays
  • Incorrect buffer delays
  • Incorrect latency numbers
  • Half cycle paths
  • Large delays and transition times
  • Missing multicycle hold
  • Path not optimized
  • Useful skew
  • Graph based analysis vs Path based analysiscle
  • Cell delay and models
  • Library attributes and modelling
  • Parasitics and SPEF
  • Slew degradation, Slew Merge
  • Graph based analysis, path based analysis
  • Multiple clocks in detail
  • Generated clock blockage, usage of clock sense
  • Clock uncertainty, latency and insertion delays
  • Virtual clocks and usage
  • Timing derate
  • Design Rules and other STA checks
  • Prelayout vs Postlayout STA
  • Inside a flop – Setup time, Hold Time, Negative setup time, Negative hold time
  • Inside a flop – Clock to Q delay, Metastability
  • Fixing setup violations
  • Hold timing checks, clear conceptual understanding
  • How is hold timing edge identified
  • Understanding hold timing report
  • Fixing hold timing
  • CRPR – Clock Reconvergence Pessimism Removal
  • Recovery, Removal Timing Check
  • Bottleneck analysis
  • Latch timing, time borrowing
  • Source synchronous clocks
  • System synchronous clocks
  • Lockup latches
  • Data to Data checks
  • Point to point delay checks
  • Crosstalk and Noise
  • Statistical Static Timing Analysis (SSTA)
  • Multimode Multi corner (MCMM) analysis
  • Merged mode analysis
  • Signoff corners and modes
  • Signoff Checklist
  • ECO
YouTube player
Demo Video
YouTube player
Demo video

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