Webinar Details
Webinar Duration: 3.5 + 3.5 hrs
Date & Time: 19th and 20th Feb Saturday & Sunday 9:30 am IST
The course is prepared by Industry Experts. The course starts at the basic level and then covers advanced topics in detail as well. Suitable for both newcomers and experienced professionals.
The webinar will cover following topics
- Introduction
- Verilog Basics – Verilog Design Styles
- Verilog Basics – Dataflow Design
- Verilog Basics – Behavioral Design
- Verilog Basics – Structural Design
- Verilog Basics – 1 bit full adder design with multiple design styles
- Verilog Basics – Verilog Testbench
- Designing Combinational Logic – 4 Valued Logic
- Designing Combinational Logic – Number represenation
- Designing Combinational Logic – Bit & Bus
- Designing Combinational Logic – Naming conventions
- Designing Combinational Logic – Bitwise operators
- Designing Combinational Logic – Arithmatic operators
- Designing Combinational Logic – Logical operators
- Designing Combinational Logic – Relational operators
- Designing Combinational Logic – Reduction Operators
- Designing Combinational Logic – Shift Operators
- Designing Combinational Logic – Concatenation operators
- Designing Combinational Logic – Repetition operators
- Designing Combinational Logic – Conditional operators
- 4 bit full adder design with testbench
- 2:1 and 4:1 multiplexer design
- 2×4,3×8,4×2 encoder and priority encoder design
- 4-bit Comparator Design
- 8-bit Barrel Shifter (Combinational Left & Right)
- Designing Arithmetic & Logic Unit (ALU)
- Clock, D-Latch and a D-Flip Flop
- D-Flip Flop vs D-Latch
- D-Latch with Asynchronous Reset (Behavioral)
- D-Flip Flop (Basic)
- Postitive Edge Triggered D-Flip Flop with Asynchronous Active High Reset
- Negative Edge Triggered D-Flip Flop with Asynchronous Active High Reset
- Postitive Edge Triggered D-Flip Flop with Asynchronous Active Low Reset
- Postitive Edge Triggered D-Flip Flop with Asynchronous Active High Set
- Synchronous D-Flip Flop with Active High Reset
- Synchronous D-Flip Flop with Active Low Reset
- Synchronous D-Flip Flop with Reset and Set
- Synchronous and Asynchronous Reset Design
- 8-bit Twin Register Set
- Designing a 5-bit Left to Right Shift Register
- Designing a 5-bit Universal Shift Register
- Designing a basic counter
- Writing a Test Bench for a Counter
- Designing an Up Counter with Load Option
- Designing an Up or Down Counter
- Designing a Modulus Counter
- Designing a Range Up Counter
- Designing a Range Up or Down Counter with Load Option
- Designing a Clock Frequency Divider (Divide by 2)
- Designing a Clock Frequency Divider (Divide by 4)
- Designing a Clock Frequency Divider (Divide by 3)
- Designing a Single Clock First In First Out (FIFO)
- Designing a Dual Clock First In First Out (FIFO)
- Memory Array Options and Definitions
- Single Port Ram
- Dual Port Ram
- True Dual Port Ram
- Mealy vs Moore Machine
- Mealy – 101 Non-Overlapping Sequence Detector
- Mealy – 011 Non-Overlapping Sequence Detector
- Mealy – 000 Non-Overlapping Sequence Detector
- Mealy – 0101 Non-Overlapping Sequence Detector
- Mealy – 11011 Non-Overlapping Sequence Detector
- Mealy – 101 Overlapping Sequence Detector
- Mealy – 011 Overlapping Sequence Detector
- Mealy – 000 Overlapping Sequence Detector
- Mealy – 0101 Overlapping Sequence Detector
- Mealy – 11011 Overlapping Sequence Detector
- Designing a Mealy Machine – Sequence Detector
- Moore – 101 Non-Overlapping Sequence Detector
- Moore – 010 Non-Overlapping Sequence Detector
- Moore – 0101 Non-Overlapping Sequence Detector
- Moore – 101 Overlapping Sequence Detector
- Moore – 010 Overlapping Sequence Detector
- Moore – 0101 Overlapping Sequence Detector
- Designing a Moore Machine – Sequence Detector
- Designing a Machine to Pick a Series of Coloured Balls and a Vending Machine
- Misc.
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