// EDA & chip design education
Every course.
Free on YouTube.
Deep, practitioner-led lessons on logic design, static timing analysis and verification, from number systems to sign-off. No paywall, no sign-up. Just subscribe and learn.
$ report_courses -all
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logic_design_fundamentals FREE
advanced_sta FREE
cdc_rdc_verification FREE
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price: 0.00 slack: MET// Latest from the channel
Fresh off the timeline
The player below always starts with the newest upload. Use the playlist icon in the player to browse every video.
// Featured
Must-watch videos
// Course tracks
Structured series, zero cost
Each track is a YouTube playlist you can follow start to finish.
01 / Foundations
Logic Design Fundamentals
Number systems, complements and binary arithmetic, logic gates, Boolean algebra, K-maps, combinational and sequential circuits, memories.
02 / Timing
Advanced Static Timing Analysis
Five modules, around 30 hours: constraints, OCV and derates, crosstalk, multi-mode multi-corner analysis and timing sign-off.
03 / Verification
CDC & RDC Verification
Clock and reset domain crossings, synchronizers and static sign-off methodology, taught by a patent holder in CDC verification.
// Open for B2B trainings
Custom training for semiconductor teams
Instructor-led programs on STA, CDC/RDC, logic design and verification methodology, tailored to your flow, tools and the experience level of your engineers. On-site or remote.
Trusted by engineering teams at
Qualcomm
Samsung
STMicroelectronics
